Shailendra Jain

According to our database1, Shailendra Jain authored at least 24 papers between 1996 and 2019.

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Bibliography

2019
Five-Level Cascaded H-Bridge MLC-Based Shunt Active Power Filter for Active Harmonics Mitigation in Distributed Network.
Journal of Circuits, Systems, and Computers, 2019

2016
A Review of Some Recently Proposed Topologies for Multilevel DC-AC Conversion.
Journal of Circuits, Systems, and Computers, 2016

Suitability of Reduced Part Count Multilevel Inverter Topologies for Grid Interfacing.
Journal of Circuits, Systems, and Computers, 2016

Unity power factor controller for neutral point clamped active front end converter with DC voltage balancing.
Proceedings of the IEEE International Conference on Industrial Technology, 2016

Wavelet based real-time power quality monitoring.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
Soft Computing Techniques for Static Series Voltage Regulator of Self Excited Induction Generator.
Journal of Circuits, Systems, and Computers, 2015

2014
A Novel Multilevel Inverter Based on Switched DC Sources.
IEEE Trans. Industrial Electronics, 2014

Carrier-Based Neutral Point Potential Regulator With Reduced Switching Losses for Three-Level Diode-Clamped Inverter.
IEEE Trans. Industrial Electronics, 2014

A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS.
IEEE Micro, 2013

Prospects of Near-Threshold Voltage Design for Green Computing.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.
Proceedings of the 25th International Conference on VLSI Design, 2012


2011
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
J. Solid-State Circuits, 2011

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
J. Solid-State Circuits, 2011

2010
HP Transforms Product Portfolio Management with Operations Research.
Interfaces, 2010

A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010


2008
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
J. Solid-State Circuits, 2008

2007
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Testing High-Speed IO Links Using On-Die Circuitry.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
A Dedicated Microcontroller based Fuzzy Controlled Shunt Active Power Filter.
Intelligent Automation & Soft Computing, 2005

2003
Broadband infrastructure - the ultimate guide to building and delivering OSS / BSS from BusinessEdge Solutions (2. ed.).
Kluwer, ISBN: 978-1-4020-7378-6, 2003

1996
Implementing Setup Optimization on the Shop Floor.
Operations Research, 1996


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