Saurabh Dighe

According to our database1, Saurabh Dighe authored at least 12 papers between 2005 and 2013.

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Bibliography

2013
IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS.
IEEE Micro, 2013

2012


2011
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits, 2011

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits, 2011

2010
The 48-core SCC Processor: the Programmer's View.
Proceedings of the Conference on High Performance Computing Networking, 2010


Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2008

2007
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators.
Proceedings of the 31st European Solid-State Circuits Conference, 2005


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