Michele Petracca

According to our database1, Michele Petracca authored at least 22 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Agile SoC Development with Open ESP.
CoRR, 2020

Agile SoC Development with Open ESP : Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Teaching Heterogeneous Computing with System-Level Design Methods.
Proceedings of the Workshop on Computer Architecture Education, 2019

2015
An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Cloud-Aided Design for Distributed Embedded Systems.
IEEE Des. Test, 2014

Accelerator Memory Reuse in the Dark Silicon Era.
IEEE Comput. Archit. Lett., 2014

2013
Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer.
IEEE J. Solid State Circuits, 2013

netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.
IEEE J. Solid State Circuits, 2012

A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm<sup>2</sup>.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Compositional system-level design exploration with planning of high-level synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Supervised design space exploration by compositional approximation of Pareto sets.
Proceedings of the 48th Design Automation Conference, 2011

An integrated four-phase buck converter delivering 1A/mm<sup>2</sup> with 700ps controller delay and network-on-chip load in 45-nm SOI.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Experiences of VoIP traffic monitoring in a commercial ISP.
Int. J. Netw. Manag., 2010

Virtual channels vs. multiple physical networks: a comparative analysis.
Proceedings of the 47th Design Automation Conference, 2010

2009
Photonic NoCs: System-Level Design Exploration.
IEEE Micro, 2009

HERO: High-speed enhanced routing operation in Ethernet NICs for software routers.
Comput. Networks, 2009

2008
Photonic networks-on-chip: Opportunities and challenges.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

Distributed flit-buffer flow control for networks-on-chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Understanding VoIP from Backbone Measurements.
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007


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