Paolo Mantovani

Maico Cassel dos Santos

Nandhini Chandramoorthy

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021

Accelerator Integration for Open-Source SoC Design.

[BibT_eX]

[DOI]

IEEE Micro, 2021

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

Agile SoC Development with Open ESP.

[BibT_eX]

[DOI]

CoRR, 2020

Agile SoC Development with Open ESP : Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning.

[BibT_eX]

[DOI]

Kuan-Lin Chiu

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Teaching Heterogeneous Computing with System-Level Design Methods.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Computer Architecture Education, 2019

Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Runtime reconfigurable memory hierarchy in embedded scalable platforms.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Accelerators and Coherence: An SoC Perspective.

[BibT_eX]

[DOI]

IEEE Micro, 2018

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

2017

Scalable System-on-Chip Design.

[BibT_eX]

[DOI]

PhD thesis, 2017

COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.

[BibT_eX]

[DOI]

Luca Piccolboni

ACM Trans. Embed. Comput. Syst., 2017

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip.

[BibT_eX]

[DOI]

Young-Jin Yoon

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Broadening the exploration of the accelerator design space in embedded scalable platforms.

[BibT_eX]

[DOI]

Luca Piccolboni

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Supercomputing, 2016

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.

[BibT_eX]

[DOI]

Kenneth L. Shepard

Proceedings of the 53rd Annual Design Automation Conference, 2016

On the design of scalable and reusable accelerators for big data applications.

[BibT_eX]

[DOI]

Qirui Xu

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

High-level synthesis of accelerators in embedded scalable platforms.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A synchronous latency-insensitive RISC for better than worst-case design.

[BibT_eX]

[DOI]

Mario R. Casu

Integr., 2015

An Analysis of Accelerator Coupling in Heterogeneous Architectures.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Accelerator Memory Reuse in the Dark Silicon Era.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2014

System-level memory optimization for high-level synthesis of component-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2012

A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

2011

Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study.

[BibT_eX]

[DOI]

Mario R. Casu

Stefano Colazzo