Yong Shim
Orcid: 0000-0002-7101-6718
According to our database1,
Yong Shim
authored at least 21 papers
between 2006 and 2024.
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Bibliography
2024
8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation.
IEEE Access, 2024
2022
A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Highly Efficient Time-Based MPPT Circuit With Extended Power Range and Minimized Tuning Switching Frequency.
IEEE Access, 2022
2021
A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator.
Sensors, 2021
An Accurate Time-Based MPPT Circuit With Two-Period Tracking Algorithm and Convergence Range Averaging Technique for IoT Applications.
IEEE Access, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets.
IEEE Trans. Biomed. Circuits Syst., 2016
Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction.
CoRR, 2016
Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets.
CoRR, 2015
2014
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.
CoRR, 2014
2013
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
IEEE J. Solid State Circuits, 2013
2012
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2006
A register controlled delay locked loop using a TDC and a new fine delay line scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006