Nabil Badereddine

J. Electron. Test., 2014

2013

A built-in scheme for testing and repairing voltage regulators of low-power srams.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Test solution for data retention faults in low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Low-power SRAMs power mode control logic: Failure analysis and test solutions.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Defect analysis in power mode control logic of low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

On using address scrambling to implement defect tolerance in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.

[BibT_eX]

[DOI]

Alberto Bosio

Luigi Dilillo

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Failure Analysis and Test Solutions for Low-Power SRAMs.

[BibT_eX]

[DOI]

Alberto Bosio

Luigi Dilillo

Aida Todri

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Detecting NBTI induced failures in SRAM core-cells.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Setting test conditions for improving SRAM reliability.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Impact of Resistive-Bridging Defects in SRAM Core-Cell.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A statistical simulation method for reliability analysis of SRAM core-cells.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2008

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.

[BibT_eX]

[DOI]

Zhanglei Wang

Krishnendu Chakrabarty

J. Electron. Test., 2008

2006

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.

[BibT_eX]

[DOI]

Hans-Joachim Wunderlich

Proceedings of the IFIP VLSI-SoC 2006, 2006

Power-Aware Test Data Compression for Embedded IP Cores.

[BibT_eX]

[DOI]

Zhanglei Wang

Krishnendu Chakrabarty

Proceedings of the 15th Asian Test Symposium, 2006

2005

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.

[BibT_eX]

[DOI]