Zhanglei Wang

According to our database1, Zhanglei Wang authored at least 24 papers between 2005 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Physical-Defect Modeling and Optimization for Fault-Insertion Test.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Diagnostic system based on support-vector machines for board-level functional diagnosis.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Board-level fault diagnosis using Bayesian inference.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Board-level fault diagnosis using an error-flow dictionary.
Proceedings of the 2011 IEEE International Test Conference, 2010

Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Deviation-Based LFSR Reseeding for Test-Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Physical defect modeling for fault insertion in system reliability test.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
Test Data Compression Using Selective Encoding of Scan Slices.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electron. Test., 2008

2007
Scan-BIST based on cluster analysis and the encoding of repeating sequences.
ACM Trans. Design Autom. Electr. Syst., 2007

Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics.
J. Electron. Test., 2007

A low cost test data compression technique for high n-detection fault coverage.
Proceedings of the 2007 IEEE International Test Conference, 2007

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.
Proceedings of the 12th European Test Symposium, 2007

SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Test set enrichment using a probabilistic fault model and the theory of output deviations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time.
Proceedings of the 15th Asian Test Symposium, 2006

Power-Aware Test Data Compression for Embedded IP Cores.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Test data compression for IP embedded cores using selective encoding of scan slices.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Built-in self-test of molecular electronics-based nanofabrics.
Proceedings of the 10th European Test Symposium, 2005


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