Laurent Souriau

Orcid: 0000-0002-5138-5938

According to our database1, Laurent Souriau authored at least 5 papers between 2018 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
SOT-MRAM 300mm integration for low power and ultrafast embedded memories.
CoRR, 2018

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


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