Shreya Kundu
According to our database1,
Shreya Kundu
authored at least 6 papers
between 2018 and 2022.
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Bibliography
2022
Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018