Paul M. Rosinger

According to our database, Paul M. Rosinger authored at least 21 papers between 2001 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.

Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., 2010

2008

Bridging Fault Test Method With Adaptive Power Management Awareness.

S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.

Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi

J. Electron. Test., 2008

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation.

Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Bridge Defect Diagnosis for Multiple-Voltage Design.

S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod

Proceedings of the 13th European Test Symposium, 2008

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.

Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.

Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Resistive Bridging Faults DFT with Adaptive Power Management Awareness.

Urban Ingelsson, Paul M. Rosinger, S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod

Proceedings of the 16th Asian Test Symposium, 2007

2006

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.

Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi

IEEE Trans. Very Large Scale Integr. Syst., 2006

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.

Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing Power Dissipation in SRAM during Test.

Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard

J. Low Power Electron., 2006

Minimizing test power in SRAM through reduction of pre-charge activity.

Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.

Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.

Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Rapid Generation of Thermal-Safe Test Schedules.

Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty

Proceedings of the 2005 Design, 2005

2004

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.

Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger

Proceedings of the 2004 Design, 2004

2002

Power profile manipulation: a new approach for reducing test application time under power constraints.

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Scan Architecture for Shift and Capture Cycle Power Reduction.

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

Power constrained test scheduling using power profile manipulation.

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001