Rainer Schaffer

According to our database, Rainer Schaffer authored at least 15 papers between 2000 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Dimensioning the heterogeneous multicluster architecture via parallelism analysis and evolutionary computing.

Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis

Proceedings of the IEEE Congress on Evolutionary Computation, 2012

Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing.

Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis

Proceedings of the IEEE Congress on Evolutionary Computation, 2012

2010

Parallelisierung von Algorithmen zur Nutzung auf Architekturen mit Teilwortparallelität.

Rainer Schaffer

PhD thesis, 2010

2008

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.

Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Massively Parallel Processor Architectures: A Co-design Approach.

Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

2006

Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism.

Rainer Schaffer, Renate Merker

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.

Sebastian Siegel, Rainer Schaffer, Renate Merker

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Derivation of Packing Instructions for Exploiting Sub-Word Parallelism.

Rainer Schaffer, Renate Merker, Francky Catthoor

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

An Architecture Description Language for Massively Parallel Processor Architectures.

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

2005

Co-Design of Massively Parallel Embedded Processor Architectures.

Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

2004

A Parallel Hardware-Software System for Signal Processing Algorithms.

Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

2003

A Hardware-Software System for Tomographic Reconstruction.

Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer

J. Circuits Syst. Comput., 2003

Causality Constraints for Processor Architectures with Sub-Word Parallelism.

Rainer Schaffer, Renate Merker, Francky Catthoor

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

Systematic Design of Programs with Sub-Word Parallelism.

Rainer Schaffer, Renate Merker, Francky Catthoor

Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

2000

Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.

Rainer Schaffer, Francky Catthoor, Renate Merker

Parallel Algorithms Appl., 2000