Sebastian Siegel

Orcid: 0000-0001-9922-4861

According to our database1, Sebastian Siegel authored at least 14 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Sequence learning in a spiking neuronal network with memristive synapses.
Neuromorph. Comput. Eng., September, 2023

System model of neuromorphic sequence learning on a memristive crossbar array.
Neuromorph. Comput. Eng., June, 2023

Demonstration of neuromorphic sequence learning on a memristive array.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2007
Abbildungsverfahren zur effizienten Implementierung rechenintensiver Algorithmen auf Prozessorarrays.
PhD thesis, 2007

Massively Parallel Processor Architectures: A Co-design Approach.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

2006
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

A Parallel Hardware-Software System for Signal Processing Algorithms.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Optimized Data-Reuse in Processor Arrays.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004


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