Dmitrij Kissler

According to our database, Dmitrij Kissler authored at least 15 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing.

Dmitrij Kissler

PhD thesis, 2012

2011

Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.

Dmitrij Kissler, Frank Hannig, Jürgen Teich

J. Low Power Electron., 2011

Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays.

Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich

IEEE Embed. Syst. Lett., 2011

2009

A holistic approach for tightly coupled reconfigurable parallel processors.

Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier

Microprocess. Microsystems, 2009

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.

Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich

J. Low Power Electron., 2009

2008

Coarse-grained reconfiguration.

Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner

Proceedings of the FPL 2008, 2008

2007

Efficient event-driven simulation of parallel processor architectures.

Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich

Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Massively Parallel Processor Architectures: A Co-design Approach.

Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.

Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement

Proceedings of the Architecture of Computing Systems, 2007

2006

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

An Architecture Description Language for Massively Parallel Processor Architectures.

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Hardware Cost Analysis for Weakly Programmable Processor Arrays.

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich

Proceedings of the International Symposium on System-on-Chip, 2006

A highly parameterizable parallel processor array architecture.

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A Generic Framework for Rapid Prototyping of System-on-Chip Designs.

Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006