Renate Merker

According to our database, Renate Merker authored at least 43 papers between 1990 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A Cost Model for Partial Dynamic Reconfiguration.

Markus Rullmann, Renate Merker

Trans. High Perform. Embed. Archit. Compil., 2011

2010

Design Methods and Tools for Improved Partial Dynamic Reconfiguration.

Markus Rullmann, Renate Merker

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.

Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Synthesis of efficiently reconfigurable datapaths for reconfigurable computing.

Markus Rullmann, Renate Merker

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Fine grain reconfigurable architectures.

Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker

Proceedings of the FPL 2008, 2008

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.

Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Massively Parallel Processor Architectures: A Co-design Approach.

Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Reconfiguration Aware Circuit Mapper for FPGAs.

Markus Rullmann, Renate Merker

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism.

Rainer Schaffer, Renate Merker

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.

Sebastian Siegel, Rainer Schaffer, Renate Merker

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Derivation of Packing Instructions for Exploiting Sub-Word Parallelism.

Rainer Schaffer, Renate Merker, Francky Catthoor

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

An Architecture Description Language for Massively Parallel Processor Architectures.

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Maximum edge matching for reconfigurable computing.

Markus Rullmann, Renate Merker

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints.

Sebastian Siegel, Renate Merker

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.

Sebastian Siegel, Renate Merker

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead.

Markus Rullmann, Renate Merker

Proceedings of the ARCS 2006, 2006

2005

Co-Design of Massively Parallel Embedded Processor Architectures.

Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching.

Markus Rullmann, Sebastian Siegel, Renate Merker

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays.

Sebastian Siegel, Renate Merker

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

A Parallel Hardware-Software System for Signal Processing Algorithms.

Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Optimal Loop Scheduling with Register Constraints Using Flow Graphs.

Jan Müller, Dirk Fimmel, Renate Merker

Proceedings of the 7th International Symposium on Parallel Architectures, 2004

Optimized Data-Reuse in Processor Arrays.

Sebastian Siegel, Renate Merker

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling.

Jan Müller, Dirk Fimmel, Renate Merker

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003

A Hardware-Software System for Tomographic Reconstruction.

Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer

J. Circuits Syst. Comput., 2003

Causality Constraints for Processor Architectures with Sub-Word Parallelism.

Rainer Schaffer, Renate Merker, Francky Catthoor

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

Systematic Design of Programs with Sub-Word Parallelism.

Rainer Schaffer, Renate Merker, Francky Catthoor

Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

2001

Design of Processor Arrays for Reconfigurable Architectures.

Dirk Fimmel, Renate Merker

J. Supercomput., 2001

2000

Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.

Rainer Schaffer, Francky Catthoor, Renate Merker

Parallel Algorithms Appl., 2000

High-Level Synthesis System (HLDESA) for Processor Arrays.

Renate Merker

Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors.

Mathias Kortke, Thomas Schmitt, Renate Merker

Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

1999

Hierarchical algorithm partitioning at system level for an improved utilization of memory structures.

Uwe Eckhardt, Renate Merker

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Localization of Data Transfer in Processor Arrays.

Dirk Fimmel, Renate Merker

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Parallelization of Algorithms for a System of Digital Signal Processors.

Mathias Kortke, Dirk Fimmel, Renate Merker

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Parallel Processor Array for Tomographic Reconstruction Algorithms.

Thomas Schmitt, Dirk Fimmel, Mathias Kortke, Renate Merker

Proceedings of the Computer Aided Systems Theory - EUROCAST'99, Vienna, Austria, September 29, 1999

1998

Determination of processor allocation in the design of processor arrays.

Dirk Fimmel, Renate Merker

Microprocess. Microsystems, 1998

Design of Processor Arrays for Real-Time Applications.

Dirk Fimmel, Renate Merker

Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997

Optimization of the Background Memory Utilization by Partitioning.

Uwe Eckhardt, Renate Merker

Proceedings of the 10th International Symposium on System Synthesis, 1997

A System for Designing Parallel Processor Arrays.

Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber

Proceedings of the Computer Aided Systems Theory, 1997

Determination of the Processor Functionality in the Design of Processor Arrays.

Dirk Fimmel, Renate Merker

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

Scheduling in Co-Partitioned Array Architectures.

Uwe Eckhardt, Renate Merker

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996

Propagation of I/O-Variables in Massively Parallel Processor Arrays.

Dirk Fimmel, Renate Merker

Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

1994

Systematic Generation of a Variety of Processor Arrays.

A. Schubert, Renate Merker, H. Schreiber

Proceedings of the Parcella 1994, 1994

1990

Systematischer Entwurf und Modellbildung systolischer Arrays.

Renate Merker

PhD thesis, 1990