Robert Giterman
Orcid: 0000-0002-1410-4746
According to our database1,
Robert Giterman
authored at least 32 papers
between 2014 and 2021.
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Bibliography
2021
Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads.
IEEE Access, 2021
Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros.
IEEE Access, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM.
Microelectron. J., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Access, 2019
Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An 800-MHz Mixed- V<sub>T</sub> 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications.
IEEE J. Solid State Circuits, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Ultra miniature offset cancelled bandgap reference with ±0.534% inaccuracy from -10°C to 110°C.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014