Shrikanth Ganapathy

According to our database, Shrikanth Ganapathy authored at least 21 papers between 2008 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Cloak: tolerating non-volatile cache read latency.

Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos

Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2021

A Method for Hiding the Increased Non-Volatile Cache Read Latency.

Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos

CoRR, 2021

2019

Assessing the Effects of Low Voltage in Branch Prediction Units.

Athanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos, Shrikanth Ganapathy, John Kalamatianos

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST.

Shrikanth Ganapathy, John Kalamatianos, Bradford M. Beckmann, Steven Raasch, Lukasz G. Szafaryn

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018

Analysis and Characterization of Ultra Low Power Branch Predictors.

Athanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos, Shrikanth Ganapathy, John Kalamatianos

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017

On Characterizing Near-Threshold SRAM Failures in FinFET Technology.

Shrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Steven Raasch

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices.

Loris Duch, Pablo García Del Valle, Shrikanth Ganapathy, Andreas Burg, David Atienza

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Approximate computing with unreliable dynamic memories.

Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Mitigating the impact of faults in unreliable memories for error-resilient applications.

Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Reliability in the face of variability in nanometer embedded memories.

Shrikanth Ganapathy

PhD thesis, 2014

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches.

Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

INFORMER: An integrated framework for early-stage memory robustness analysis.

Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Effectiveness of hybrid recovery techniques on parametric failures.

Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio

Proceedings of the International Symposium on Quality Electronic Design, 2013

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.

Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells.

Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González

Integr., 2012

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance.

Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.

Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

MODEST: a model for energy estimation under spatio-temporal variability.

Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.

Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio

Proceedings of the Design, Automation and Test in Europe, 2010

2008

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system.

Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Design for Testability of Functional Cores in High Performance Node Architectures.

Nagarajan Venkateswaran, Karthik Chandrasekar, Shrikanth Ganapathy

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008