Robert J. Polastre

According to our database1, Robert J. Polastre authored at least 9 papers between 1992 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2008
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections.
IBM J. Res. Dev., 2008

Three-dimensional silicon integration.
IBM J. Res. Dev., 2008

3D chip stacking with C4 technology.
IBM J. Res. Dev., 2008

2006
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias.
IEEE J. Solid State Circuits, 2006

2005
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection.
IBM J. Res. Dev., 2005

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1998
Thin-film-transistor process-characterization test structures.
IBM J. Res. Dev., 1998

A 10.5-in.-diagonal SXGA active-matrix display.
IBM J. Res. Dev., 1998

1992
Functional testing of TFT/LCD arrays.
IBM J. Res. Dev., 1992


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