Christian W. Baks
According to our database1,
Christian W. Baks
authored at least 39 papers
between 2005 and 2023.
Collaborative distances:
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Bibliography
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas.
IEEE J. Solid State Circuits, 2022
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.
IEEE J. Solid State Circuits, 2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2020
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
A Nonblocking 4×4 Mach-Zehnder Switch with Integrated Gain and Nanosecond-Scale Reconfiguration Time.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
2018
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018
Antenna-in-package design and module integration for millimeter-wave communication and 5G.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
System-Level Demonstration of a Dynamically Reconfigured Burst-Mode Link Using a Nanosecond Si-Photonic Switch.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
2017
IEEE J. Solid State Circuits, 2017
Driver-integrated 56-Gb/s segmented electrode silicon Mach Zehnder modulator using optical-domain equalization.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017
2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
2015
IEEE J. Solid State Circuits, 2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
Exploring the limits of high-speed receivers for multimode VCSEL-based optical links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Monolithically integrated silicon nanophotonics receiver in 90nm CMOS technology node.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
2012
Electrical Performance of the Recessed Probe Launch Technique for Measurement of Embedded Multilayer Structures.
IEEE Trans. Instrum. Meas., 2012
JOCN, 2012
2009
Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link.
IEEE J. Solid State Circuits, 2009
2008
A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2005
Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005