Ruijun Ma

According to our database, Ruijun Ma authored at least 15 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults.

Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Ruijun Ma, Tianming Ni, Xiaoqing Wen, Hiroshi Takahashi

CoRR, September, 2025

Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design.

Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet.

Hui Xu, Yong Xue, Yu Zhang, Xia Sun, Jiale Li, Ruijun Ma, Huaguo Liang, Zhengfeng Huang

Integr., 2025

Semi-supervised lithography hotspot detection based on feature fusion and residual attention.

Hui Xu, Xinzhong Xiao, Wenxin Huang, Ruijun Ma, Fuxin Tang, Pan Qi, Ye Yuan, Huaguo Liang

Integr., 2025

2024

A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches.

Hui Xu, Xuewei Qin, Ruijun Ma, Chaoming Liu, Shuo Zhu, Jun Wang, Huaguo Liang

J. Electron. Test., February, 2024

Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments.

Hui Xu, Chaoming Liu, Ruijun Ma, Tai Song, Zhengfeng Huang, Jun Wang, Xuewei Qin, Yu Xia

Microelectron. J., January, 2024

A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements.

Hui Xu, Lin Tang, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Tianming Ni, Jiuqi Li, Xiaodong Ai

Microelectron. J., 2024

A Low-Cost Triple-Node-Upset Self-Recovery Latch Design.

Hui Xu, Yu Xia, Ruijun Ma, Huaguo Liang, Zhenfeng Huang

J. Circuits Syst. Comput., 2024

Design of novel low cost triple-node-upset self-recoverable hardened latch.

Hui Xu, Shuo Zhu, Ruijun Ma, Zhengfeng Huang, Huaguo Liang, Haojie Sun, Chaoming Liu

Integr., 2024

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs.

Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy.

Hui Xu, Jing Zhou, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Chaoming Liu

Integr., 2023

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell.

Stefan Holst, Ruijun Ma, Xiaoqing Wen, Aibin Yan, Hui Xu

Proceedings of the IEEE European Test Symposium, 2023

2022

Evaluation and Test of Production Defects in Hardened Latches.

Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu

IEICE Trans. Inf. Syst., 2022

2019

STAHL: A Novel Scan-Test-Aware Hardened Latch Design.

Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

The impact of production defects on the soft-error tolerance of hardened latches.

Stefan Holst, Ruijun Ma, Xiaoqing Wen

Proceedings of the 23rd IEEE European Test Symposium, 2018