Senling Wang

Orcid: 0000-0002-7129-8380

According to our database1, Senling Wang authored at least 26 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device.
IEICE Trans. Inf. Syst., January, 2024

2023
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Test Point Insertion for Multi-Cycle Power-On Self-Test.
ACM Trans. Design Autom. Electr. Syst., 2023

SASL-JTAG: A Light-Weight Dependable JTAG.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

QR-Code with Superimposed Text.
Proceedings of the 24st Asia-Pacific Network Operations and Management Symposium, 2023

2022
Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2020
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips.
IEEE Trans. Emerg. Top. Comput., 2020

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST.
IEICE Trans. Inf. Syst., 2020

2018
Automotive Functional Safety Assurance by POST with Sequential Observation.
IEEE Des. Test, 2018

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line.
IEICE Trans. Inf. Syst., 2017

Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD).
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.
IPSJ Trans. Syst. LSI Des. Methodol., 2016

Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip.
J. Low Power Electron., 2015

Diagnosis of Delay Faults Considering Hazards.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2013
Scan-Out Power Reduction for Logic BIST.
IEICE Trans. Inf. Syst., 2013

2012
A Scan-Out Power Reduction Method for Multi-cycle BIST.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Low Power BIST for Scan-Shift and Capture Power.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Genetic algorithm based approach for segmented testing.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011


  Loading...