Rabie Ben Atitallah
According to our database1, Rabie Ben Atitallah authored at least 53 papers between 2006 and 2019.
Legend:Book In proceedings Article PhD thesis Other
Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks.
J. Electronic Imaging, 2019
ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures.
Int. J. Reconfig. Comp., 2019
A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis.
Computación y Sistemas, 2019
FPGA-Centric Design Process for Avionic Simulation and Test.
IEEE Trans. Aerospace and Electronic Systems, 2018
Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays.
J. Intelligent Manufacturing, 2018
An Embedded Multi-Sensor Data Fusion Design for Vehicle Perception Tasks.
Multi-Sensor Fusion for Obstacle Detection and Recognition: A Belief-Based Approach.
Proceedings of the 21st International Conference on Information Fusion, 2018
Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems.
Signal Processing Systems, 2017
New MIP model for multiprocessor scheduling problem with communication delays.
Optimization Letters, 2017
Multi-level energy/power-aware design methodology for MPSoC.
J. Parallel Distributed Comput., 2017
Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application.
I. J. Circuit Theory and Applications, 2017
An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
A Comprehensive Approach for Camera/LIDAR Frame Alignment.
Proceedings of the Informatics in Control, Automation and Robotics, 2017
An Extrinsic Sensor Calibration Framework for Sensor-fusion based Autonomous Vehicle Perception.
Proceedings of the 14th International Conference on Informatics in Control, 2017
FPGA-Centric High Performance Embedded Computing: Challenges and Trends.
Proceedings of the Euromicro Conference on Digital System Design, 2017
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
An Optimized Software Radio Application Using a Dynamic Slack Reclamation Technique on a Real Platform OMAP 3530.
Proceedings of the 14th IEEE/ACS International Conference on Computer Systems and Applications, 2017
AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Using hardware parallelism for reducing power consumption in video streaming applications.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Communication-centric design for FMC based I/O system.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
A generic pixel distribution architecture for parallel video processing.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
System-level power estimation tool for embedded processor based platforms.
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014
Early power-aware Design Space Exploration for embedded systems: MPEG-2 case study.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
PETS: Power and energy estimation tool at system-level.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Redefining the role of FPGAs in the next generation avionic systems (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Model-driven design flow for distributed control in reconfigurable FPGA systems.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Dynamic reconfiguration and low power design : towards self-adaptive massively parallel embedded systems.
An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC.
IEEE Trans. Industrial Informatics, 2013
Hybrid and multicore optimized architectures for test and simulation systems.
Proceedings of the 6th International ICST Conference on Simulation Tools and Techniques, 2013
Optimization of Matching and Scheduling on Heterogeneous CPU/FPGA Architectures.
Proceedings of the 7th IFAC Conference on Manufacturing Modelling, Management, and Control, 2013
Heterogeneous CPU/FPGA Reconfigurable Computing System for Avionic Test Application.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
A fast MPSoC virtual prototyping for intensive signal processing applications.
Microprocess. Microsystems, 2012
Abstract Clock-Based Design of a JPEG Encoder.
Embedded Systems Letters, 2012
Dynamic reconfiguration of modular I/O IP cores for avionic applications.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
An efficient power estimation methodology for complex RISC processor-based platforms.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Open-People: Open Power and Energy Optimization PLatform and Estimator.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Open-people: An open platform for estimation and optimizations of energy consumption.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
A Model-Driven Design Framework for Massively Parallel Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2011
A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design.
EURASIP J. Emb. Sys., 2011
Dynamically reconfigurable architecture for a driver assistant system.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
A prototyping environment for high performance reconfigurable computing.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
A system level power consumption estimation for MPSoC.
Proceedings of the 2011 International Symposium on System on Chip, 2011
Hybrid system level power consumption estimation for FPGA-based MPSoC.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Fast and accurate hybrid power estimation methodology for embedded systems.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Toward generic and adaptive avionic test systems.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
An efficient design methodology for hybrid avionic test systems.
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010
An Improved Automotive Multiple Target Tracking System Design.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Multilevel MPSOC simulation using an MDE approach.
Proceedings of the 2007 IEEE International SOC Conference, 2007
An MPSoC Performance Estimation Framework Using Transaction Level Modeling.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
Estimating Energy Consumption for an MPSoC Architectural Exploration.
Proceedings of the Architecture of Computing Systems, 2006