Nai-Chen Cheng

According to our database, Nai-Chen Cheng authored at least 10 papers between 2007 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

8.2 A 32Gb/s 12.35Tb/s/mm² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging.

Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating.

Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan J. Drake, Chin-Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A 0.296pJ/bit 17.9Tb/s/mm² Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.

Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2016

A 0.8V, 43.5μW ECG signal acquisition IC with a referenceless time-to-digital converter.

Shu-Hsuan Lin, Fu-To Lin, Nai-Chen Cheng, Yu-Te Liao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Invited - Wireless sensor nodes for environmental monitoring in internet of things.

Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh

Proceedings of the 53rd Annual Design Automation Conference, 2016

2013

A 32.4 μW RF front end for 2.4 GHz wake-up receiver.

Yu-Lin Tsou, Nai-Chen Daniel Cheng, Christina F. Jou

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS.

Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng

Proceedings of the ESSCIRC 2013, 2013

2010

An embedded wide-range and high-resolution CLOCK jitter measurement circuit.

Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen

Proceedings of the Design, Automation and Test in Europe, 2010

2008

Experimental Results of Built-In Jitter Measurement for Gigahertz Clock.

Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement.

Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen

Proceedings of the 16th Asian Test Symposium, 2007