Sheng Yang

Affiliations:
  • University of Southampton, Department of Electronics and Computer Science, UK
  • University of Southern California, Department of Electrical Engineering, Los Angeles, CA, USA (PhD 2004)


According to our database1, Sheng Yang authored at least 24 papers between 2002 and 2018.

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Timeline

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Bibliography

2018
Runtime Performance and Power Optimization of Parallel Disparity Estimation on Many-Core Platforms.
ACM Trans. Embed. Comput. Syst., 2018

A model-based framework for software portability and verification in embedded power management systems.
J. Syst. Archit., 2018

2017
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Aging Benefits in Nanometer CMOS Designs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Voltage, Throughput, Power, Reliability, and Multicore Scaling.
Computer, 2017

2016
Reliable Power Gating With NBTI Aging Benefits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Application-specific memory protection policies for energy-efficient reliable design.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Adaptive energy minimization of embedded heterogeneous systems using regression-based learning.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems.
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

2014
High Quality Testing of Grid Style Power Gating.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2011
Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Improved DFT for Testing Power Switches.
Proceedings of the 16th European Test Symposium, 2011

2010
Scan based methodology for reliable state retention power gating designs.
Proceedings of the Design, Automation and Test in Europe, 2010

2005
Progressive lossless 3D mesh encoder with octree-based space partitioning.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A progressive view-dependent technique for interactive 3-D mesh transmission.
IEEE Trans. Circuits Syst. Video Technol., 2004

Joint mesh-texture optimization for progressive transmission.
Proceedings of the Visual Communications and Image Processing 2004, 2004

Optimized mesh and texture multiplexing for progressive textured model transmission.
Proceedings of the 12th ACM International Conference on Multimedia, 2004

Progressive coding of 3D textured graphic model via joint mesh-texture optimization.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Robust graphics streaming in walkthrough virtual environments via wireless channels.
Proceedings of the Global Telecommunications Conference, 2003

2002
View-dependent progressive mesh coding based on partitioning.
Proceedings of the Visual Communications and Image Processing 2002, 2002


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