Shota Konno
Orcid: 0000-0003-3125-3580
According to our database1,
Shota Konno
authored at least 6 papers
between 2020 and 2024.
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Bibliography
2024
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.
IEEE J. Solid State Circuits, January, 2024
2023
A 2.38 MCells/mm<sup>2</sup> 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2020
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020