Muya Chang

According to our database1, Muya Chang authored at least 13 papers between 2018 and 2021.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Hardware Dynamical System for Solving Optimization Problems.
PhD thesis, 2021

A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.
IEEE J. Solid State Circuits, 2021

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers.
IEEE J. Solid State Circuits, 2020

A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics.
IEEE J. Solid State Circuits, 2020

A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture.
Proceedings of the IEEE International Conference on Acoustics, 2019

Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations.
Proceedings of the 76th Device Research Conference, 2018


  Loading...