Soroush Abbaspour

According to our database1, Soroush Abbaspour authored at least 21 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Efficient compression and handling of current source model library waveforms.
Proceedings of the Design, Automation and Test in Europe, 2009

A moment-based effective characterization waveform for static timing analysis.
Proceedings of the 46th Design Automation Conference, 2009

2008
Constrained aggressor set selection for maximum coupling noise.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Driver waveform computation for timing analysis with multiple voltage threshold driver models.
Proceedings of the 45th Design Automation Conference, 2008

Towards a more physical approach to gate modeling for timing, noise, and power.
Proceedings of the 45th Design Automation Conference, 2008

2007
Parameterized Non-Gaussian Variational Gate Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Compact modeling of variational waveforms.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Fast Interconnect and Gate Timing Analysis for Performance Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2006

SACI: statistical static timing analysis of coupled interconnects.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Non-gaussian statistical interconnect timing analysis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Parameterized block-based non-gaussian statistical gate timing analysis.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
VGTA: Variation Aware Gate Timing Analysis.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Interconnect energy dissipation in high-speed ULSI circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Gate delay calculation considering the crosstalk capacitances.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Buffer sizing for minimum energy-delay product by using an approximating polynomial.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Calculating the effective capacitance for the RC interconnect in VDSM technologies.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


  Loading...