Steffen Tarnick

According to our database1, Steffen Tarnick authored at least 21 papers between 1992 and 2011.

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Bibliography

2011
An Accumulator - Based Test-Per-Clock Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Design of embedded constant weight code checkers based on averaging operations.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2008
Self-Testing Embedded Borden <i>t</i> -UED Code Checkers for <i>t</i> = 2<sup> <i>k</i> </sup> <i>q</i> - 1 with <i>q</i> = 2<sup> <i>m</i> </sup> - 1.
J. Electron. Test., 2008

A Low-Cost Accumulator-Based Test Pattern Generation Architecture.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Embedded Borden 2-UED Code Checkers.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes.
J. Electron. Test., 2005

2004
Design of Embedded Self-Testing Checkers for <i>t</i>-UED and BUED Codes.
J. Electron. Test., 2004

Single-Output Embedded Checkers for Systematic Unordered Codes.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003
A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes.
Proceedings of the 2003 Design, 2003

2000
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes.
J. Electron. Test., 2000

1999
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998
Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability.
VLSI Design, 1998

Embedded self-testing checkers for low-cost arithmetic codes.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996
Self-Checking Comparator with One Periodic Output.
IEEE Trans. Computers, 1996

1995
Data compression techniques for concurrent error detection and built-in self test.
PhD thesis, 1995

Controllable self-checking checkers for conditional concurrent checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.
IEEE Trans. Computers, 1995

Pattern generation for a deterministic BIST scheme.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1992
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992


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