Takeshi Ohkawa

According to our database1, Takeshi Ohkawa authored at least 46 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Genetic Node-Mapping Methods for Rapid Collective Communications.
IEICE Transactions, 2020

2019
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept.
IEICE Transactions, 2019

Automatic Generation Tool of FPGA Components for Robots.
IEICE Transactions, 2019

Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster.
IEICE Transactions, 2019

Directive-Based Parallelization of For-Loops at LLVM IR Level.
Proceedings of the 20th IEEE/ACIS International Conference on Software Engineering, 2019

Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

High level synthesis of ROS protocol interpretation and communication circuit for FPGA.
Proceedings of the 2nd International Workshop on Robotics Software Engineering, 2019

Design and Development of Networked Multiple FPGA Components for Autonomous Tiny Robot Car.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster.
Proceedings of the Advanced Information Networking and Applications, 2019

2018
A Genetic Approach for Accelerating Communication Performance by Node Mapping.
IEICE Transactions, 2018

FPGA Components for Integrating FPGAs into Robot Systems.
IEICE Transactions, 2018

Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster.
Proceedings of the 11th Workshop on General Purpose Processing using GPUs, 2018

Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster.
Proceedings of the 2018 Workshop on Advanced Tools, 2018

An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration.
Wireless Personal Communications, 2017

A Static Packet Scheduling Approach for Fast Collective Communication by Using PSO.
IEICE Transactions, 2017

Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Translation Method of ARM Machine Code to LLVM-IR for Binary Code Parallelization and Optimization.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

2016
Enhancing Entropy Throttling: New Classes of Injection Control in Interconnection Networks.
IEICE Transactions, 2016

Architecture exploration of intelligent robot system using ros-compliant FPGA component.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

cReComp: Automated Design Tool for ROS-Compliant FPGA Component.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Introducing PSO for Optimal Packet Scheduling of Collective Communication.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015
Relaxing Heavy Congestion by State Propagation.
JIP, 2015

Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems.
CoRR, 2015

Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory.
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

An Android cluster system capable of dynamic node reconfiguration.
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015

Entropy Throttling: Towards Global Congestion Control of Interconnection Networks.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations.
Proceedings of the Third International Symposium on Computing and Networking, 2015

2013
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application.
SIGARCH Computer Architecture News, 2013

A Cellular Automata Approach for Large-Scale Interconnection Network Simulation.
Proceedings of the First International Symposium on Computing and Networking, 2013

Efficient Data Communication Using Dynamic Switching of Compression Method.
Proceedings of the First International Symposium on Computing and Networking, 2013

Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History.
Proceedings of the First International Symposium on Computing and Networking, 2013

Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind.
Proceedings of the First International Symposium on Computing and Networking, 2013

A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
Proposal of Incremental Software Simulation for Reduction of Evaluation Time.
Proceedings of the Third International Conference on Networking and Computing, 2012

Comparative Study of Path Prediction Method for Speculative Loop Execution.
Proceedings of the Third International Conference on Networking and Computing, 2012

2011
COOL interconnect low power interconnection technology for scalable 3D LSI design.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2010
A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique.
IEICE Transactions, 2010

2004
An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004


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