Takeshi Kataoka

According to our database, Takeshi Kataoka authored at least 7 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.

Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

IEEE J. Solid State Circuits, 2015

2014

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.

Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.

Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori

IEEE Micro, 2013

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.

Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Keynote & invited speaker's biography [7 biographies].

Bert Gyselinckx, Hiroshi Kanayama, Michael McCool, Shintaro Momose, Takeshi Kataoka, James Myers, Toshio Yoshida

Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

2007

A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery.

Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2006

Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications.

Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura

IEICE Trans. Electron., 2006