Mitsuhiko Igarashi

According to our database1, Mitsuhiko Igarashi authored at least 9 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.
IEEE J. Solid State Circuits, 2015

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Assessment of reliability impact on GHz processors with moderate overdrive.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012
28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


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