Ryo Mori

According to our database1, Ryo Mori authored at least 7 papers between 2007 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2015
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.
IEEE J. Solid State Circuits, 2015

2014
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

High density and reliable packaging technology with Non Conductive Film for 3D/TSV.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2007
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.
IEEE J. Solid State Circuits, 2007


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