Kazuki Fukuoka

According to our database1, Kazuki Fukuoka authored at least 13 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard.
IEEE J. Solid State Circuits, 2017

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.
IEEE J. Solid State Circuits, 2015

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.
IEEE Micro, 2013

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.
Proceedings of the Integrated Circuit and System Design, 2004

A technique for high-speed circuits on SOI using look-ahead type active body bias control.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Leakage power reduction for clock gating scheme on PD-SOI.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004