Kazuki Fukuoka

According to our database, Kazuki Fukuoka authored at least 14 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power.

Kenichi Shimada, Keiichiro Sano, Kazuki Fukuoka, Hiroshi Morita, Masayuki Daito, Tatsuya Kamei, Hiroyuki Hamasaki, Yasuhisa Shimazaki

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2019

A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCU.

Toshifumi Uemura, Yuko Kitaji, Kazuki Fukuoka

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2017

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard.

Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima

IEEE J. Solid State Circuits, 2017

2016

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM.

Takao Nomura, Ryo Mori, Koji Takayanagi, Kazuki Fukuoka, Koji Nii

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.

Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.

Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

IEEE J. Solid State Circuits, 2015

2014

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.

Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.

Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori

IEEE Micro, 2013

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.

Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.

Takao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology.

Kazuki Fukuoka, Ryo Mori, A. Kato, Motoshige Igarashi, Koji Shibutani, T. Yamaki, Shinji Tanaka, Koji Nii, Sadayuki Morita, Takao Koike, Noriaki Sakamoto

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2004

A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.

Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada

Proceedings of the Integrated Circuit and System Design, 2004

A technique for high-speed circuits on SOI using look-ahead type active body bias control.

Masaaki Iijima, Katsuya Fujita, Kazuki Fukuoka, Masahiro Numa, Keisuke Yamamoto, Kengo Takata

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Leakage power reduction for clock gating scheme on PD-SOI.

Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004