Henri-Pierre Charles

According to our database1, Henri-Pierre Charles authored at least 32 papers between 1991 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


Automated Software Protection for the Masses Against Side-Channel Attacks.
TACO, 2019

Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization.
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Automatic Application of Software Countermeasures Against Physical Attacks.
Proceedings of the Cyber-Physical Systems Security., 2018

Software platform dedicated for in-memory computing circuit evaluation.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

A New Compilation Flow for Software-Defined Radio Applications on Heterogeneous MPSoCs.
TACO, 2016

Pushing the Limits of Online Auto-Tuning: Machine Code Optimization in Short-Running Kernels.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Self-optimisation using runtime code generation for wireless sensor networks.
Proceedings of the 17th International Conference on Distributed Computing and Networking, 2016

Is dynamic compilation possible for embedded systems?
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT.
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015

Hardware Acceleration of Red-Black Tree Management and Application to Just-In-Time Compilation.
Signal Processing Systems, 2014

Performance comparison between Java and JNI for optimal implementation of computational micro-kernels.
CoRR, 2014

Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem5.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

deGoal a Tool to Embed Dynamic Code Generators into Applications.
Proceedings of the Compiler Construction - 23rd International Conference, 2014

A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoC.
Proceedings of the 2014 International Conference on Compilers, 2014

Scilab on a hybrid platform.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Improving performance of optimized kernels through fast instantiations of templates.
Concurrency and Computation: Practice and Experience, 2009

Optimizing code through iterative specialization.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

An Effective Automated Approach to Specialization of Code.
Proceedings of the Languages and Compilers for Parallel Computing, 2007

Hybrid Specialization: A Trade-off Between Static and Dynamic Specialization.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Applying Code Specialization to FFT Libraries for Integral Parameters.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

A Software-only Compression System for Trading-off Performance and Code Size.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005

Data cache management on EPIC architecture: optimizing memory access for image processing.
SIGARCH Computer Architecture News, 2004

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999



Scheduling a Scattering-Gathering Sequence on Hypercubes.
Parallel Processing Letters, 1993

A Portable Parallel Toolkit for 3D Image Processing.
European Transactions on Telecommunications, 1992

Loop unrolling for processors with instruction cache.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991