Tiago T. Jost

According to our database, Tiago T. Jost authored at least 13 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

GPU Code Generation of Cardiac Electrophysiology Simulation with MLIR.

Tiago Trevisan Jost, Arun Thangamani, Raphaël Colin, Vincent Loechner, Stéphane Genaud, Bérenger Bramas

Proceedings of the Euro-Par 2023: Parallel Processing - 29th International Conference on Parallel and Distributed Computing, Limassol, Cyprus, August 28, 2023

Lifting Code Generation of Cardiac Physiology Simulation to Novel Compiler Technology.

Arun Thangamani, Tiago Trevisan Jost, Vincent Loechner, Stéphane Genaud, Bérenger Bramas

Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

2021

Compilation and optimizations for variable precision floating-Point arithmetic : from language and libraries to code generation. (Compilation et optimisations pour l'arithmétique à virgule flottante en précision variable : du langage et des bibliothèques à la génération de code).

Tiago Trevisan Jost

PhD thesis, 2021

Seamless Compiler Integration of Variable Precision Floating-Point Arithmetic.

Tiago Trevisan Jost, Yves Durand, Christian Fabre, Albert Cohen, Frédéric Pétrot

Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

2020

SoMMA: A software-managed memory architecture for multi-issue processors.

Tiago Trevisan Jost, Gabriel Luca Nazar, Luigi Carro

Microprocess. Microsystems, 2020

VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic.

Tiago T. Jost, Yves Durand, Christian Fabre, Albert Cohen, Frédéric Pétrot

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

Byte-Aware Floating-point Operations through a UNUM Computing Unit.

Andrea Bocco, Tiago T. Jost, Albert Cohen, Florent de Dinechin, Yves Durand, Christian Fabre

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Evaluation of variable bit-width units in a RISC-V processor for approximate computing.

Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018

Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform.

Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs.

Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong, Luigi Carro, Antonio C. S. Beck

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

An energy-efficient memory hierarchy for multi-issue processors.

Tiago T. Jost, Gabriel L. Nazar, Luigi Carro

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Improving performance in VLIW soft-core processors through software-controlled scratchpads.

Tiago T. Jost, Gabriel L. Nazar, Luigi Carro

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Scalable memory architecture for soft-core processors.

Tiago T. Jost, Gabriel L. Nazar, Luigi Carro

Proceedings of the 34th IEEE International Conference on Computer Design, 2016