Tomasz S. Czajkowski

According to our database1, Tomasz S. Czajkowski authored at least 20 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
ACPO: AI-Enabled Compiler-Driven Program Optimization.
CoRR, 2023

Efficient Data Streaming for a Tightly-Coupled Coarse-Grained Reconfigurable Array.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

2018
Real-Time Simulation of Animated Characters Crowd in Unreal Engine 4.
Proceedings of the Computer Vision and Graphics - International Conference, 2018

Modeling and Rendering of Volumetric Clouds in Real-Time with Unreal Engine 4.
Proceedings of the Computer Vision and Graphics - International Conference, 2018

High-level synthesis of software-customizable floating-point cores.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2015
High-Level Design Tools for Floating Point FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Silicon Verification using High-Level Design Tools (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems.
ACM Trans. Embed. Comput. Syst., 2013

Harnessing the power of FPGAs using altera's OpenCL compiler.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

From software to accelerators with LegUp high-level synthesis.
Proceedings of the International Conference on Compilers, 2013

2012
From opencl to high-performance hardware on FPGAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Impact of FPGA architecture on resource sharing in high-level synthesis.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
LegUp: high-level synthesis for FPGA-based processor/accelerator systems.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast toggle rate computation for FPGA circuits.
Proceedings of the FPL 2008, 2008

2007
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2004
A synthesis oriented omniscient manual editor.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004


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