Wei Shi

According to our database, Wei Shi authored at least 21 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

An Energy-Efficient and Artifact-Resilient ASIC for Simultaneous Neural Recording and Optogenetic Stimulation.

Linran Zhao, Yan Gong, Raymond G. Stephany, Wei Shi, Wen Li, Yaoyao Jia

IEEE Trans. Biomed. Circuits Syst., August, 2025

Session-Level Dynamic Ad Load Optimization using Offline Robust Reinforcement Learning.

Tao Liu, Qi Xu, Wei Shi, Zhigang Hua, Shuang Yang

Proceedings of the 31st ACM SIGKDD Conference on Knowledge Discovery and Data Mining, V.1, 2025

2024

33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend.

Linran Zhao, Wei Shi, Yan Gong, Xiang Liu, Wen Li, Yaoyao Jia

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis.

Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Ads Supply Personalization via Doubly Robust Learning.

Wei Shi, Chen Fu, Qi Xu, Sanjian Chen, Jizhe Zhang, Qinqin Zhu, Zhigang Hua, Shuang Yang

Proceedings of the 33rd ACM International Conference on Information and Knowledge Management, 2024

2023

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.

Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, September, 2023

A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation.

Linran Zhao, Yan Gong, Wei Shi, Raymond Stephany, Wen Li, Yaoyao Jia

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization.

Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL.

Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

A 0.37mm² 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2^nd-order Vector-Quantizer DEM.

Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits.

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.

Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.

Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR.

Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.

Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis.

Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.

Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu

IEEE J. Solid State Circuits, 2019

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier.

Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.01mm² 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.

Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019