Xingyun Qi

According to our database, Xingyun Qi authored at least 20 papers between 2006 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers.

Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver.

Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai

Microelectron. J., 2025

2024

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.

Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang

Microelectron. J., 2024

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process.

Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao

IEICE Electron. Express, 2024

A Comprehensive Simulation Framework for CXL Disaggregated Memory.

Yanjing Wang, Lizhou Wu, Wentao Hong, Yang Ou, Zicong Wang, Sunfeng Gao, Jie Zhang, Sheng Ma, Dezun Dong, Xingyun Qi, Mingche Lai, Nong Xiao

CoRR, 2024

Automatic Implementation of Large-Scale CNNs on FPGA Cluster Based on HLS4ML.

Yihang Lu, Xingyun Qi, Yuan Li, Mingche Lai, Yankang Zhao, Zhenqi Li, Hanyuan Li, Qiang Wang

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2024

A High-performance Hardware Accelerator for Genome Alignment.

Haoyu Liao, Yuan Li, Qiang Wang, Mingche Lai, Hui Su, Ziwen Li, Xingyun Qi

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2024

Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms.

Haoyu Liao, Yuan Li, Puguang Liu, Qiang Wang, Mingche Lai, Xingyun Qi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver.

Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2022

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.

Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi

Microelectron. J., 2022

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.

Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu

IEEE Access, 2022

2021

Microarchitecture of a Configurable High-Radix Router for the Post-Moore Era.

Yi Dai, Kai Lu, Junsheng Chang, Xingyun Qi, Jijun Cao, Jianmin Zhang

Proceedings of the High Performance Computing - 36th International Conference, 2021

MPICC: Multi-Path INT-Based Congestion Control in Datacenter Networks.

Guoyuan Yuan, Dezun Dong, Xingyun Qi, Baokang Zhao

Proceedings of the Network and Parallel Computing, 2021

PFT: A Congestion Avoidance Method based on Proactive Flow Throttling at Endpoints.

Xingyun Qi, Mingche Lai, Dezun Dong, Yi Dai, Junsheng Chang, Jijun Cao

Proceedings of the 17th IFIP/IEEE International Symposium on Integrated Network Management, 2021

2020

MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test.

Xingyun Qi, Pingjing Lu, Jijun Cao, Yi Dai, Mingche Lai, Junsheng Chang

Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

Optimal Implementation of In-Band Network Management for High-Radix Switches.

Jijun Cao, Mingche Lai, Xingyun Qi, Yi Dai, Zhengbin Pang

Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2017

A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design.

Yi Dai, Kefei Wang, Gang Qu, Liquan Xiao, Dezun Dong, Xingyun Qi

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2009

BOIN: A novel Bufferless Optical Interconnection Network for high performance computer.

Xingyun Qi, Wei Yang, Yongran Chen, Qiang Dou, Quanyou Feng, Wenhua Dou

Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009

A Fault Tolerant Bufferless Optical Interconnection Network.

Xingyun Qi, Quanyou Feng, Yongran Chen, Qiang Dou, Wenhua Dou

Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009

2006

PMPS(3): A Performance Model of Parallel Systems.

Yongran Chen, Xingyun Qi, Yue Qian, Wenhua Dou

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006