Xu Cheng

According to our database1, Xu Cheng authored at least 22 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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On csauthors.net:

Bibliography

2020
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
A 24-bit sigma-delta ADC with configurable chopping scheme.
IEICE Electron. Express, 2019

2016
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors.
Microelectron. J., 2016

2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Non-binary digital calibration for split-capacitor DAC in SAR ADC.
IEICE Electron. Express, 2015

2014
A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express, 2014

2013
A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme.
Microelectron. J., 2013

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electron. Express, 2012

2011
A low power 1.0 GHz VCO in 65nm-CMOS LP-process.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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