Yunbo Huang
Orcid: 0000-0002-1355-7583
According to our database1,
Yunbo Huang authored at least 24 papers
between 2010 and 2026.
Collaborative distances:
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Bibliography
2026
A 22.4-25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction.
IEEE J. Solid State Circuits, June, 2026
A 5.4-GHz reference-sampling PLL-sub-sampling DLL cascaded frequency synthesizer achieving 85.7-fs RMS jitter in 65-nm CMOS.
Microelectron. J., 2026
Microelectron. J., 2026
25.10 A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 2-GHz 5.06-mW Phase Accumulator Employing Dynamic Regulation for High-Speed Direct Digital Frequency Synthesizers in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A D-Band Power Amplifier with A Novel Gain-Boosting Structure Achieving 15.8-dB Gain and 23.9-GHz Bandwidth in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2<sup>nd</sup> Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Neural Comput. Appl., August, 2024
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
7.4 A 0.027mm<sup>2</sup> 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
A 3.78-GHz Type-I Sampling PLL With a Fully Passive K<sub>PD</sub>-Doubled Primary-Secondary S-PD Measuring 39.6-fs<sub>RMS</sub> Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs<sub>RMS</sub>Jitter, -258.7-dB FOM, and -75.17-dBc Reference Spur.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
AAIA: an efficient aggregation scheme against inverting attack for federated learning.
Int. J. Inf. Sec., 2023
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2<sup>nd</sup>-Harmonic Output.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2021
A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM.
IEEE Trans. Circuits Syst., 2020
2018
Microelectron. Reliab., 2018
Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment.
Microelectron. Reliab., 2018
2011
Comput. Ind. Eng., 2011
2010
A multi-class preemptive priority cognitive radio system with random interruption discipline.
Proceedings of the 5th International Conference on Queueing Theory and Network Applications, 2010