Yatish Turakhia
Orcid: 0000-0001-5600-2900
According to our database1,
Yatish Turakhia
authored at least 23 papers
between 2013 and 2025.
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Bibliography
2025
Commun. ACM, May, 2025
2024
DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics.
CoRR, 2024
The Genomic Computing Revolution: Defining the Next Decades of Accelerating Genomics.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
Bioinform., September, 2023
Bioinform., September, 2023
2022
PLoS Comput. Biol., 2022
J. Open Source Softw., 2022
matOptimize: a parallel tree optimization method enables online phylogenetics for SARS-CoV-2.
Bioinform., 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
2021
ShUShER: private browser-based placement of sensitive genome samples on phylogenetic trees.
J. Open Source Softw., 2021
2020
Proceedings of the International Conference for High Performance Computing, 2020
2019
Proceedings of the Algorithms and Architectures for Parallel Processing, 2019
Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications.
IEEE Trans. Computers, 2017
2016
Thread Progress Equalization: Dynamically Adaptive Power and Performance Optimization of Multi-threaded Applications.
CoRR, 2016
2015
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.
CoRR, 2015
2013
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors.
Proceedings of the Design, Automation and Test in Europe, 2013
HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013