Yeonggeun Song
Orcid: 0000-0002-6021-8912
According to our database1,
Yeonggeun Song
authored at least 6 papers
between 2019 and 2025.
Collaborative distances:
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Bibliography
2025
30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2023
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2019
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs, 2019