Yi Shen

According to our database1, Yi Shen authored at least 12 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits, 2019

A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Analysis and optimization of the two-stage pipelined SAR ADCs.
Microelectron. J., 2016

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS.
Microelectron. J., 2016

A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor.
IET Circuits Devices Syst., 2014