Chung-Len Lee

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2014
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2011
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design.
IEICE Trans. Electron., 2011

2008
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2005
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults.
IEEE Des. Test Comput., 2005

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A New Path Delay Test Scheme Based on Path Delay Inertia.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
An On-Chip Jitter Measurement Circuit for the PLL.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2001
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
J. Inf. Sci. Eng., 2000

1999
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1995
On Designing of 4-Valued Memory with Double-Gate TFT.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Panel: New Research Problems in the Emerging Test Technology.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1991
A Probabilistic Testability Measure for Delay Faults.
Proceedings of the 28th Design Automation Conference, 1991


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