Yitao Ma
Orcid: 0000-0003-4004-0245Affiliations:
- Tohoku University, Japan
According to our database1,
Yitao Ma
authored at least 15 papers
between 2011 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society.
IEEE Trans. Ind. Informatics, August, 2023
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3.
Neural Comput. Appl., May, 2023
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2023
2022
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.
IEEE Trans. Ind. Informatics, 2022
2021
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits, 2021
2020
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering.
IEEE Trans. Veh. Technol., 2020
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate.
IEEE Access, 2020
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application.
IEEE Access, 2020
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2016
Proc. IEEE, 2016
2013
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching.
Proceedings of the International SoC Design Conference, 2011