Yu-Ching Liao

Orcid: 0009-0006-8198-9739

According to our database1, Yu-Ching Liao authored at least 9 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Research on Ultra-Large Sensing Range and High Linearity Cavity Sensing Devices.
IEEE Access, 2026

2024
Reliable Low-Voltage FeRAM Capacitors for High-Speed Dense Embedded Memory in Advanced CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
Event Source Page Discovery via Policy-Based RL with Multi-task Neural Sequence Model.
Proceedings of the Web Information Systems Engineering - WISE 2022, 2022

Chat-log Disentanglement via Same-Thread Classification and Direct-Reply Prediction.
Proceedings of the 36th Pacific Asia Conference on Language, Information and Computation, 2022

Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators.
Proceedings of the IEEE International Memory Workshop, 2022

2021
Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits.
CoRR, 2021

2015
Multiple Silicon Nanowires with Enzymatic Modification for Measuring Glucose Concentration.
Micromachines, 2015

2013
A layout-aware automatic sizing approach for retargeting analog integrated circuits.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

LASER: layout-aware analog synthesis environment on laker.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013


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