Yandong Luo
Orcid: 0000-0002-3331-743X
According to our database1,
Yandong Luo
authored at least 23 papers
between 2018 and 2024.
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Bibliography
2024
A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS).
IEEE Trans. Emerg. Top. Comput., 2024
2023
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
IEEE Trans. Computers, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators.
Proceedings of the IEEE International Memory Workshop, 2022
2021
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Computers, 2021
Swarm Robot Exploration Strategy for Path Formation Tasks Inspired by Physarum polycephalum.
Complex., 2021
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses.
IEEE Trans. Computers, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro, 2019
MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations.
Proceedings of the International Conference on Neuromorphic Systems, 2019
2018
Proceedings of the Intelligent Computing Theories and Application, 2018