Yutaka Yamada

Orcid: 0000-0002-5636-3367

According to our database1, Yutaka Yamada authored at least 16 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Links

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Bibliography

2022
Trend Prediction of Students' Mock Examination Results Using Matrix Completion.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2020
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.
IEEE J. Solid State Circuits, 2020

2019
A 20.5TOPS and 217.3GOPS/mm<sup>2</sup> Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Performance Prediction Method of Examinees Based on Matrix Completion.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

2015
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011
Virtual Screening for Ligands of the Insect Molting Hormone Receptor.
J. Chem. Inf. Model., 2011

FlexGrip™: A small and high-performance programmable hardware for highly sequential application.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2009
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IEEE Trans. Parallel Distributed Syst., 2009

2006
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.
IEEE Trans. Parallel Distributed Syst., 2006

An implementation of hardware accelerator using dynamically reconfigurable architecture.
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2005
Evaluation of vibration in many positions by SOM.
Artif. Life Robotics, 2005

Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005

2004
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Stream applications on the dynamically reconfigurable processor.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.
Proceedings of the Embedded and Ubiquitous Computing, 2004


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