Zhang Zhang

According to our database, Zhang Zhang authored at least 47 papers between 2011 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing.

Zhang Zhang, Zhihao Chen, Jiedong Wang, Guangjun Xie, Gang Liu

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation.

Annan Wang, Yuchen Sun, Zhang Zhang

Microelectron. J., 2025

A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain.

Sikai Chen, Peng Zhang, Lumiao Zhang, Zhang Zhang

Microelectron. J., 2025

A Lightweight Authenticated Encryption Algorithm Based on Compact CLEFIA Block Cipher.

Meiyu Liang, Tao Ji, Yin Yuan, Xin Cheng, Zhang Zhang, Lixiang Ma

J. Circuits Syst. Comput., 2025

2024

Memristor-Based Neural Network Circuit of Associative Memory With Occasion Setting.

Juntao Han, Xin Cheng, Guangjun Xie, Junwei Sun, Gang Liu, Zhang Zhang

IEEE Trans. Cogn. Dev. Syst., June, 2024

Voltage-Resistance-Adaptive MPPT Circuit for Energy Harvesting.

Zhang Zhang, Annan Wang, Hongtao Ren, Guangjun Xie, Xin Cheng

IEEE Des. Test, June, 2024

A gate-tunable memristor emulator for motion detection.

Zhang Zhang, Yongbo Ma, Gang Shi, Chao Li, Gang Liu

Int. J. Circuit Theory Appl., May, 2024

Cascaded refinement residual attention network for image outpainting.

Yizhong Yang, Shanshan Yao, Changjiang Liu, Zhang Zhang, Guangjun Xie

Multim. Syst., April, 2024

A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory.

Zhang Zhang, Zhihao Chen, Sikai Chen, Guangjun Xie, Jianmin Zeng, Gang Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A multi-scale feature fusion spatial-channel attention model for background subtraction.

Yizhong Yang, Tingting Xia, Dajin Li, Zhang Zhang, Guangjun Xie

Multim. Syst., December, 2023

Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON-Galois/Counter Mode.

Xin Cheng, Yixuan Xu, Kefan Wang, Yongqiang Zhang, Bin Li, Zhang Zhang

Int. J. Circuit Theory Appl., December, 2023

A multi-scale inputs and labels model for background subtraction.

Yizhong Yang, Dajin Li, Xiang Li, Zhang Zhang, Guangjun Xie

Signal Image Video Process., November, 2023

Cascaded deep residual learning network for single image dehazing.

Yizhong Yang, Ce Hou, Haixia Huang, Zhang Zhang, Guangjun Xie

Multim. Syst., August, 2023

An FPGA-based memristor emulator for artificial neural network.

Zhang Zhang, Chao Li, Weiqi Zhang, Jing Zhou, Gang Liu

Microelectron. J., 2023

2022

MSE-Net: generative image inpainting with multi-scale encoder.

Yizhong Yang, Zhihang Cheng, Haotian Yu, Yongqiang Zhang, Xin Cheng, Zhang Zhang, Guangjun Xie

Vis. Comput., 2022

STPNet: A Spatial-Temporal Propagation Network for Background Subtraction.

Yizhong Yang, Jiahao Ruan, Yongqiang Zhang, Xin Cheng, Zhang Zhang, Guangjun Xie

IEEE Trans. Circuits Syst. Video Technol., 2022

Gate-Controlled Memristor FPGA Model for Quantified Neural Network.

Zhang Zhang, Ao Xu, Chao Li, Yadong Wei, Zhiheng Ge, Xin Cheng, Gang Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Mathematical analysis and circuit emulator design of the three-valued memristor.

Zhang Zhang, Ao Xu, Chao Li, Gang Liu, Xin Cheng

Integr., 2022

Reconfigurable multivalued memristor FPGA model for digital recognition.

Zhang Zhang, Ao Xu, Hongtao Ren, Gang Liu, Xin Cheng

Int. J. Circuit Theory Appl., 2022

2021

A novel control circuit for piezoelectric energy harvesting.

Zhang Zhang, Zechen Tang, Zhang Yunfeng, Xin Cheng, Guangjun Xie

Microelectron. J., 2021

Using correction parameters to improve real-time video interpolation in low-cost VLSI implementation.

Haowei Guan, Zhang Zhang, Xin Cheng, Yizhong Yang, Guangjun Xie

Microelectron. J., 2021

A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration.

Xin Cheng, Haowen Zhu, Yixuan Xu, Yongqiang Zhang, Hao Xiao, Zhang Zhang

Microelectron. J., 2021

An output capacitor-less low-dropout regulator with wide load capacitance and current ranges.

Zhang Zhang, Shu Xu, Hongyuan Wu, Guangjun Xie, Xin Cheng

Int. J. Circuit Theory Appl., 2021

A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation.

Xin Cheng, Bin Li, Haowen Zhu, Yongqiang Zhang, Zhang Zhang

Int. J. Circuit Theory Appl., 2021

A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator.

Xin Cheng, Haowen Zhu, Xinyi Xing, Yunfeng Zhang, Yongqiang Zhang, Guangjun Xie, Zhang Zhang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line.

Xin Cheng, Wanjing Shao, Lixin Xu, Yongqiang Zhang, Guangjun Xie, Zhang Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

CFE: a convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata.

Feifei Deng, Guangjun Xie, Xin Cheng, Zhang Zhang, Yongqiang Zhang

IET Circuits Devices Syst., 2020

Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation.

Hao Xiao, Yanming Fan, Fen Ge, Zhang Zhang, Xin Cheng

IEICE Trans. Inf. Syst., 2020

DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing.

Jianmin Zeng, Zhang Zhang, Runhao Chen, Shiyue Liang, Tianlin Cao, Zhiyi Yu, Xin Cheng, Guangjun Xie

IEICE Electron. Express, 2020

High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique.

Xin Cheng, Wanjing Shao, Yongqiang Zhang, Jianmin Zeng, Zhang Zhang

IEICE Electron. Express, 2020

2019

Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata.

Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng, Guangjun Xie

J. Circuits Syst. Comput., 2019

A 24-bit sigma-delta ADC with configurable chopping scheme.

Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng

IEICE Electron. Express, 2019

A Fast and Accurate Edge Detection Algorithm for Real-Time Deep-Space Autonomous Optical Navigation.

Hao Xiao, Yanming Fan, Zhang Zhang, Xin Cheng

Proceedings of the 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2019

A 30MHz Delay-Line-Based Buck Converter with 5.7%-94.8% Switching Duty Cycle.

Zhang Zhang, Shu Xu, Fangzhou Yao, Guangjun Xie, Xin Cheng

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

A Single-Input Multi-Output Piezoelectric Energy Harvesting System Combining with P-SSHI and Cold Startup Circuit.

Xin Cheng, Bo Cheng, Zechen Tang, Yongqiang Zhang, Zhang Zhang

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Countering power analysis attacks by exploiting characteristics of multicore processors.

Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng

IEICE Electron. Express, 2018

A 15 W wireless power receiver with an improved full-wave synchronous rectifier.

Chubin Wu, Guangjun Xie, Zhang Zhang, Xin Cheng, Tairan Fei, Jianmin Zeng, Xiaoyang Zeng

IEICE Electron. Express, 2018

A Qi compatible wireless power receiver with integrated full-wave synchronous rectifier.

Chubin Wu, Zhang Zhang, Jianmin Zeng, Xin Cheng, Guangjun Xie

Sci. China Inf. Sci., 2018

Study of High Voltage Deep Brain Stimulation.

Zhang Zhang, Lingling Wei, Xiaojuan Zhou, Taolue Zhu, Guangjun Xie, Xin Cheng

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator.

Xin Cheng, Hongyu Liang, Longjie Du, Zhang Zhang, Maoxiang Yi, Guangjun Xie

J. Circuits Syst. Comput., 2017

A multi-core-based heterogeneous parallel turbo decoder.

Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu

IEICE Electron. Express, 2017

2015

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.

Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.

Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach.

Xin Cheng, Guangjun Xie, Zhang Zhang, Yizhong Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.

Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.

Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng

IEICE Electron. Express, 2012

2011

A low power 1.0 GHz VCO in 65nm-CMOS LP-process.

Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011