According to our database1, Zhenghong Jiang authored at least 6 papers between 2014 and 2019.
Legend:Book In proceedings Article PhD thesis Other
Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
High-level synthesis with timing-sensitive information flow enforcement.
Proceedings of the International Conference on Computer-Aided Design, 2018
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels.
SIGARCH Computer Architecture News, 2016
A technology mapper for depth-constrained FPGA logic cells.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Exploring architecture parameters for dual-output LUT based FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014