Zhenghong Jiang

According to our database, Zhenghong Jiang authored at least 9 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Load balancing in virtual machines of cloud environments using two-level particle swarm optimization algorithm.

Chunrong Zhou, Zhenghong Jiang

J. Intell. Fuzzy Syst., December, 2023

Application of improved Naive Bayes classification algorithm in 5G signaling analysis.

Wanwan Wang, Yu Duan, Longhan Cao, Zhenghong Jiang

J. Supercomput., April, 2023

2021

Efficient Loop Closure Detection Method for Lidar SLAM in Challenging Environment.

Yang Li, Wanbiao Lin, Tianjun Zha, Zhenghong Jiang, Peiwen Li, Lei Sun

Proceedings of the 6th International Conference on Control, Robotics and Cybernetics, 2021

2019

Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES.

Zhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

High-level synthesis with timing-sensitive information flow enforcement.

Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.

Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels.

Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang

SIGARCH Comput. Archit. News, 2016

2015

A technology mapper for depth-constrained FPGA logic cells.

Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Exploring architecture parameters for dual-output LUT based FPGAs.

Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014