Alexander V. Rylyakov

According to our database1, Alexander V. Rylyakov authored at least 48 papers between 2003 and 2020.

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Bibliography

2020
A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength.
IEEE J. Solid State Circuits, 2020

2019
34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers.
IEEE J. Solid State Circuits, 2019


Monolithically-Integrated 50 Gbps 2pJ/bit Photoreceiver with Cherry-Hooper TIA in 250nm BiCMOS Technology.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018


A 34Gbaud Linear Transimpedance Amplifier with Automatic Gain Control for 200Gb/s DP-16QAM Optical Coherent Receivers.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

2016
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.
IEEE J. Solid State Circuits, 2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

A 25 Gb/s burst-mode receiver for low latency photonic switch networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

High speed circuits for short reach optical communications.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A 4-λ, 40Gb/s/λ bandwidth extension of multimode fiber in the 850nm range.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A Throughput-Optimized Optical Network for Data-Intensive Computing.
IEEE Micro, 2014

A 28 GHz Hybrid PLL in 32 nm SOI CMOS.
IEEE J. Solid State Circuits, 2014

64Gb/s transmission over 57m MMF using an NRZ modulated 850nm VCSEL.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

Low power CMOS-driven 1060 nm multimode optical link.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

Exploring the limits of high-speed receivers for multimode VCSEL-based optical links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.
IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.
IEEE J. Solid State Circuits, 2013

Optical receivers using DFE-IIR equalization.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers.
IEEE J. Solid State Circuits, 2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


2011
A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link.
IEEE J. Solid State Circuits, 2009

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI.
IEEE J. Solid State Circuits, 2008

A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions.
IEEE J. Solid State Circuits, 2007

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.
IEEE J. Solid State Circuits, 2007

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003
SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev., 2003


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